The present invention relates to a semiconductor device, and, more particularly, to a semiconductor device (read channel LSI) in a digital magnetic storage device, which demodulates and decodes a read signal from a read head using a decision feedback equalizer or a semiconductor device in a base band transmission device, which demodulates and decodes a received signal.
A hard disk device has a read channel IC including an A/D (Analog-to-Digital) converter, which converts an analog signal read from a hard disk by a read head to a digital signal, and an equalizer which decodes the digital signal, generating a decoded digital signal.
As the recording density of data and the read speed increase, there is more interest in a decision feedback equalizer (DFE) than a PRML (Partial Response and Maximum-Likelihood detection) type waveform equalizer. The PRML type waveform equalizer needs a high-precision digital filter and equalizer filter, which prevent increasing the processing speed and circuit miniaturization. On the other hand, the DFE has a relatively simple circuit structure, and thus provides a preferable way to improve the reading speed and miniaturization.
As shown in FIG. 1, the read head provides a reproduced waveform which has a voltage corresponding to change in a magnetic field on a recording medium. When the bias point of the reproduced waveform is shifted due to some disturbance factor, a reproduced waveform having a vertical asymmetry, shown by the broken line in FIG. 3, is formed. When the reproduced waveform has an asymmetry, its electromagnetic conversion characteristic is represented by an approximation curve as shown in FIG. 2. In FIG. 2, the straight line indicates the input/output waveform characteristic of an ideal reproduced waveform.
The asymmetry of the reproduced waveform from the head and the insufficient characteristic adjusting performance of the equalizer produce a deformation in the equalized waveform generated by the DFE. This deformation is detected as the difference between a target equalized waveform and the actual equalized waveform.
The asymmetry of the reproduced waveform also leads to an error in a decision made by the equalizer, thereby increasing the bit error rate of decoded signals. To cope with this shortcoming, a conventional read channel LSI corrects the asymmetry of the reproduced waveform using the following schemes.
Scheme 1: A digital signal output from the A/D converter is divided into two components with respect to a base line of a predetermined level (e.g., the zero level) and correction values are added to the two divided digital signals.
Scheme 2: The input amplitude is divided into a predetermined number of sub-amplitudes and correction values set for the respective sub-amplitudes are added to the digital signal while approximating the input/output characteristic curve in each sub-amplitude using polygonal lines.
These schemes are carried out by measuring the bit error rate of an output signal (disk read data) with respect to an input signal (disk write data) and adjusting the characteristic of the equalizer based on the measuring result. As it is necessary to repeatedly measure the bit error rate and adjust the characteristic of the equalizer, the adjusting takes a considerable amount of time.
Scheme 1 corrects only the peak value of a reproduced waveform, so its correcting effect is small. Because correction values are preset in the scheme 2, this scheme cannot cope with a change in input signal.
Japanese Unexamined Patent Publication (KOKAI) No. Hei 10-83626 discloses a DFE which comprises a forward equalizer (forward filter), an adder, a code detector (decision unit) and a back equalizer (feedback filter). Each of the forward equalizer and back equalizer includes an FIR (Finite Impulse Response) filter, and the characteristics of both equalizers or coefficients are automatically adjusted based on the detection result (reproduction state) from the code detector. This structure reduces reproduction errors caused by noise from a head unit (MR head) having a manufacturing error or an asymmetric characteristic. That is, this structure suppresses reproduction errors which are produced by factors, such as use conditions, manufacturing variations and time-dependent changes.
The forward filter and feedback filter have a close correlation. Specifically, the coefficient of the feedback filter is determined by the characteristic of the forward filter. To change the coefficient of the forward filter, therefore, the coefficient of the feedback filter should be changed too. Arithmetic circuits are used to alter the coefficients of both the forward filter and feedback filter. The number of arithmetic circuits provided should be equal to the number of taps of each equalizer. As the number of taps increases, the number of the arithmetic circuits also increases, making the circuit area of the DFE larger.
If the gains of both the forward filter and feedback filter are increased to quickly converge the coefficients of both filters to the optimal coefficients, the feedback loop becomes unstable. Adaptive equalization of the forward filter and feedback filter, by way of contrast, stabilizes the feedback loop but takes time for the coefficients to converge. To improve the precision of the forward filter, it is desirable to increase the number of forward filters. Because the increase in the number of forward filters enhances the gain of the forward filter, it is necessary to cope with an abrupt change in filter output.
Further, the maximum likelihood decoder that is used in the PRML system involves soft decision, whereas the DFE involves hard decision. This requires that the gain of the DFE be enhanced to suppress decision errors. When an unexpected deformation is superimposed on the input signal of the DFE, therefore, the number of equalization errors increases, making the adaptive equalization difficult. As apparent from the above, the DFE involves a difficult adjustment to make the coefficients converge and takes a significant time to optimize the adjustment of the coefficients.
There is a variation in the analog front end characteristic of the DFE on the input side. To optimize the filter coefficients in accordance with this variation, the DFE performs coefficient training. Because the training work is performed on the forward filter and the feedback filter, it takes time and effort.
Accordingly, it is a first object of the present invention to provide a semiconductor device or circuit which corrects the asymmetry of a reproduced waveform with high precision.
It is a second object of this invention to provide a semiconductor device or circuit having a decision feedback equalizer whose characteristic is easily adjusted.
In one aspect of the present invention, a semiconductor circuit is provided that includes a decision feedback equalizer for waveform-equalizing a corrected input signal and generating a waveform-equalized signal. The equalizer compares the waveform-equalized signal with a predetermined reference level to generate a decision signal having first and second decision values and an error signal between the waveform-equalized signal and the decision signal. A dispersion-value calculator is connected to the decision feedback equalizer, calculates a first dispersion value of the decision signal having the first decision value and a second dispersion value of the decision signal having the second decision value using the error signal, and produces a compensation signal using the first and second dispersion values. An asymmetry compensator is connected to the decision feedback equalizer and the dispersion-value calculator, receives an input signal and correcting an asymmetry of the input signal in accordance with the compensation signal and supplies the corrected input signal to the decision feedback equalizer.
In another aspect of the present invention, a semiconductor circuit is provided that includes an analog-to-digital (A/D) converter for converting an analog input signal to a digital input signal with an intermediate reference voltage as a base line. A decision feedback equalizer waveform-equalizes a corrected digital input signal and generates a waveform-equalized signal. The equalizer compares the waveform-equalized signal with a predetermined reference level and produces a decision signal having first and second decision values and an error signal between the waveform-equalized signal and the decision signal. A dispersion-value calculator is connected to the decision feedback equalizer, calculates a first dispersion value of the decision signal having the first decision value and a second dispersion value of the decision signal having the second decision value using the error signal and produces a compensation signal using the first and second dispersion values. An asymmetry compensator is connected between the decision feedback equalizer and the A/D converter, receives the compensation signal from the dispersion-value calculator, corrects an asymmetry of the digital input signal using the compensation signal and supplies the corrected digital input signal to the decision feedback equalizer. A base-line compensation detector is connected to the decision feedback equalizer and computes a base-line compensation value using the waveform-equalized signal. A digital-to-analog (D/A) converter is connected to the base-line compensation detector and the A/D converter, produces the intermediate reference voltage in accordance with the base-line compensation value and supplies the intermediate reference voltage to the A/D converter.
In yet another aspect of the present invention, a semiconductor circuit is provided that includes a finite impulse response (FIR) equalizer for equalizing a waveform of a digital signal to produce an equalized digital signal. A decision feedback equalizer is connected to the FIR equalizer and compares the equalized digital signal with a predetermined reference level to produce a decision signal.
In another aspect of the present invention, a decision feedback equalizer is provided that includes a finite impulse response (FIR) equalizer for equalizing a waveform of a digital signal to produce an equalized digital signal. A forward filter is connected to the FIR equalizer and filters the equalized digital signal using a first coefficient to produce a filtered digital signal. An adder is connected to the forward filter and adds the filtered digital signal and a feedback signal to produce an added signal. A decision circuit is connected to the adder and compares the added signal with a predetermined reference level to produce a decision signal. A feedback filter is connected to the decision circuit and the adder, filters the decision signal using a second coefficient to produce the feedback signal and supplies the feedback signal to the adder.
Other aspects and advantages of the invention will become apparent from the following description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention.